SWRF=0, WDTRF=0, REERF=0, BUSSRF=0, BUSMRF=0, RPERF=0, IWDTRF=0, SPERF=0
Reset Status Register 1
| IWDTRF | Independent Watchdog Timer Reset Detect FlagNote: Only 0 can be written to clear the flag. The reset flag must be written as 0 after the reset flag is read as 1. 0 (0): Independent watchdog timer reset not detected. 1 (1): Independent watchdog timer reset detected. |
| WDTRF | Watchdog Timer Reset Detect FlagNote: Only 0 can be written to clear the flag. The reset flag must be written as 0 after the reset flag is read as 1. 0 (0): Watchdog timer reset not detected. 1 (1): Watchdog timer reset detected. |
| SWRF | Software Reset Detect FlagNote: Only 0 can be written to clear the flag. The reset flag must be written as 0 after the reset flag is read as 1. 0 (0): Software reset not detected. 1 (1): Software reset detected. |
| Reserved | These bits are read as 00000. The write value should be 00000. |
| RPERF | RAM Parity Error Reset Detect FlagNote: Only 0 can be written to clear the flag. The reset flag must be written as 0 after the reset flag is read as 1. 0 (0): RAM parity error reset not detected. 1 (1): RAM parity error reset detected. |
| REERF | RAM ECC Error Reset Detect FlagNote: Only 0 can be written to clear the flag. The reset flag must be written as 0 after the reset flag is read as 1. 0 (0): RAM ECC error reset not detected. 1 (1): RAM ECC error reset detected. |
| BUSSRF | Bus Slave MPU Reset Detect FlagNote: Only 0 can be written to clear the flag. The reset flag must be written as 0 after the reset flag is read as 1. 0 (0): Bus Slave MPU reset not detected. 1 (1): Bus Slave MPU reset detected. |
| BUSMRF | Bus Master MPU Reset Detect FlagNote: Only 0 can be written to clear the flag. The reset flag must be written as 0 after the reset flag is read as 1. 0 (0): Bus Master MPU reset not detected. 1 (1): Bus Master MPU reset detected. |
| SPERF | SP Error Reset Detect FlagNote: Only 0 can be written to clear the flag. The reset flag must be written as 0 after the reset flag is read as 1. 0 (0): SP error reset not detected. 1 (1): SP error reset detected. |
| Reserved | These bits are read as 000. The write value should be 000. |